AI INFRASTRUCTURE THESIS
Why Post-CUDA Domain-Specific Silicon Wins Inference Economics at Scale
AUTHORING PARTNER
Julian Sterling
PARTNER TITLE
Managing Partner
CORE THESIS METRIC
3.8x Tokens / Watt
EXECUTIVE INVESTMENT THESIS
As enterprise AI shifts 85% of compute spend from frontier training to continuous agentic inference, memory-bandwidth-first architectures break general-purpose GPU lock-in.
ARCHITECTURAL & MARKET ANALYSIS
Training rewards universal flexibility; production inference rewards deterministic SRAM locality and compiler-scheduled dataflow. Startups pairing MLIR compiler stacks with deterministic silicon achieve 3.8x higher tokens per watt.
WHAT WE LOOK FOR AT PRE-SEED & SEED
Compiler-first founding teams (MLIR/Triton) · Working FPGA or kernel emulation benchmarks · Clear path to zero-code-change PyTorch/vLLM drop-in adoption.
01 // APEX VENTURES
DeepTech Seed & Series A
$420M Fund IV leading $1.5M–$12M checks in AI silicon, robotics, computational bio, and grid infrastructure.
02 // CAPITAL & PORTFOLIO
Mandate & Ledger
Clean 1x non-participating preferred governance plus $350K non-dilutive H100 compute access.
03 // PARTNERSHIP
Bench & Research
Every memo read directly by former-founder General Partners in San Francisco, New York, and Zurich.
04 // GOVERNANCE & DOCS
Disclosures & Manual
SEC/Advisers Act non-solicitation notices, founder confidentiality, and 12-station owner manual.
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FUND IV DEPLOYING // 48-HR GP REVIEW SLA